1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming electronic fuses for providing device internal programming capabilities in complex integrated circuits.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are decreased with the introduction of every new circuit generation, to provide currently available integrated circuits with an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size of the transistors is commonly associated with an increased switching speed, thereby enhancing signal processing performance. In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors and the like, are typically formed in integrated circuits that are used for a plurality of purposes, such as for decoupling.
Due to the reduced dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated micro-controller devices, an increasing amount of storage capacity may be provided on chip with the CPU core, thereby also significantly enhancing the overall performance of modern computer devices.
In modern integrated circuits, minimal features sizes have now reached approximately 50 nm and less, thereby providing the possibility of incorporating various functional circuit portions at a given chip area, wherein, however, the various circuit portions may have a significantly different performance, for instance with respect to lifetime, reliability and the like. For example, the operating speed of a digital circuit portion, such as a CPU core and the like, may depend on the configuration of the individual transistor elements and also on the characteristics of the metallization system, which may include a plurality of stacked metallization layers so as to comply with a required complex circuit layout. Thus, highly sophisticated manufacturing techniques may be required in order to provide the minimum critical feature sizes of the speed critical circuit components. For example, sophisticated digital circuitry may be used on the basis of field effect transistors, which represent circuit components in which conductivity of a channel region is controlled on the basis of a gate electrode that is separated from the channel region by a thin dielectric material. Performance of the individual field effect transistors is determined by, among other things, the capability of the transistor to switch from a high impedance state into a low impedance state at high speeds, wherein a sufficiently high current may also be driven in the low impedance state. This drive current capability is determined by, among other things, the length of the conductive channel that forms in the channel region upon application of an appropriate control voltage to the gate electrode. For this reason, and in view of the increasing overall packing density of sophisticated semiconductor devices, the channel length, and thus the length, of the gate electrode is continuously being reduced, which, in turn, may require an appropriate adaptation of the capacitive coupling of the gate electrode to the channel region. Consequently, the thickness of the gate dielectric material may also have to be reduced in order to maintain controllability of the conductive channel at a desired high level. However, the shrinkage of the gate dielectric thickness may be associated with an exponential increase of the leakage currents, which may directly tunnel through the thin gate dielectric material, thereby contributing to enhanced power consumption and thus waste heat, which may contribute to sophisticated conditions during operation of the semiconductor device. Moreover, charge carriers may be injected into the gate dielectric material and may also contribute to a significant degradation of transistor characteristics, such as threshold voltage of the transistors, thereby also contributing to variability of the transistor characteristics over the lifetime of the product. Consequently, reliability and performance of certain sophisticated circuit portions may be determined by material characteristics and process techniques for forming highly sophisticated circuit elements, while other circuit portions may include less critical devices which may thus provide a different behavior over the lifetime compared to critical circuit portions. Consequently, the combination of the various circuit portions in a single semiconductor device may result in a significant different behavior with respect to performance and reliability, wherein, also, the variations of the overall manufacturing process flow may contribute to a further discrepancy between the various circuit portions. For these reasons, in complex integrated circuits, frequently, additional mechanisms may be implemented so as to allow the circuit itself to adapt performance of certain circuit portions to comply with the performance of other circuit portions, for instance after completing the manufacturing process and/or during use of the semiconductor device, for instance when certain critical circuit portions may no longer comply with corresponding performance criteria, thereby requiring an adaptation of certain circuit portions, such as re-adjusting an internal voltage supply, re-adjusting the overall circuit speed and the like.
For this purpose, so-called electronic fuses or e-fuses may be provided in the semiconductor devices, which may represent electronic switches that may be activated once in order to provide a desired circuit adaptation. Hence, the electronic fuses may be considered as having a high impedance state, which may typically also represent a “programmed” state, and may have a low impedance state, typically representing a non-programmed state of the electronic fuse. Since these electronic fuses may have a significant influence on the overall behavior of the entire integrated circuit, a reliable detection of the non-programmed and the programmed state may have to be guaranteed, which may have to be accomplished on the basis of appropriately designed logic circuitry. Furthermore, since typically these electronic fuses may be actuated only once over the lifetime of the semiconductor device under consideration, a corresponding programming activity may have to ensure that a desired programmed state of the electronic fuse is reliably generated in order to provide well-defined conditions for the further operational lifetime of the device. With the continuous shrinkage of critical device dimensions in sophisticated semiconductor devices, however, the reliability of the programming of corresponding electronic fuses may require tightly set margins for the corresponding voltages and currents used to program the electronic fuses, which may not be compatible with the overall specifications of the semiconductor devices or may at least have a severe influence on the flexibility of operating the device.
In conventional strategies, the fuses are formed on the basis of a semiconductor material, such as polysilicon and the like, as may typically also be used for forming conductive lines in the device level of the semiconductor device, for instance for gate electrode structures of field effect transistors, wherein the per se negative effect of electromigration, in combination with a charge carrier depletion in the semiconductor material, may be taken advantage of in order to initiate a significant deterioration of the electronic fuse by applying a current for programming the fuse into a high impedance state. As is well known, electromigration is a phenomenon in which a high current density in DC operated conductive lines may result in a “diffusion” of metal atoms caused by the momentum transfer of the high density electron flow. In polysilicon lines, typically, a metal silicide material is provided to enhance the conductivity of the semiconductor-based material and a pronounced electromigration effect may, thus, intentionally be initiated in the metal silicide material, thereby increasingly contributing to a metal depletion at the cathode, while a material agglomeration is observed towards the anode. Furthermore, the electromigration effect may further be increased by locally creating elevated temperatures, which may be accomplished by locally providing a desired high resistance for a given total current that is to be driven through the electronic fuse. Consequently, appropriate lateral dimensions for fuse bodies, i.e., the portions of the electronic fuses in which an electromigration effect and, thus, the line degradation is to be initiated, are provided for a given material composition and thickness of the electronic fuses, in accordance with the overall process strategy for forming the sophisticated gate electrode structures of the field effect transistors. For example, the cross-sectional area of the fuse bodies may be reduced by selecting a minimum width of the fuse bodies, while at the same time the length of the fuse bodies may be increased, thereby increasing the overall electromigration effect.
Due to the increasing overall complexity of semiconductor devices, however, an increased number of electronic fuses has to be provided, which, however, may result in a significant consumption of valuable chip area in the device level of the semiconductor devices. Furthermore, recently, very complex gate electrode structures are being implemented in sophisticated semiconductor devices in order to enhance transistor performance, wherein the conventional gate materials, such as silicon dioxide as a gate dielectric and polysilicon in combination with a metal silicide as an electrode material, are replaced by a high-k dielectric material in combination with an electrode metal, such as aluminum and the like. As a consequence, materials of improved conductivity may be implemented in the fuse bodies, unless additional significant efforts have to be made so as to locally provide the conventional polysilicon/metal silicide material system for the electronic fuses. Thus, the incorporation of highly conductive metals, such as aluminum and the like, in the device level and the demand for further increasing the overall packing density in semiconductor devices have recently resulted in the concept of providing electrically programmable fuses on the basis of metals, thereby also considering the possibility of implementing “three-dimensional” fuses, which may, thus, be provided in the metallization system of the semiconductor device.
In complex semiconductor devices, typically, metallization systems, i.e., a plurality of stacked metallization levels, are provided, in which metal lines provide the inner-level electrical connection, while so-called vias, i.e., “vertical” interconnect structures, may provide the intra-level connection, thereby providing the complex interconnect network in order to electrically connect the individual circuit elements provided in the device level according to the required circuit layout. The metal lines and vias typically comprise a highly conductive metal, such as aluminum, or, in very complex integrated circuits, copper, which may exhibit a reduced electromigration effect and an overall higher conductivity compared to aluminum. Due to copper's characteristic to readily diffuse in a plurality of well-established dielectric materials, such as silicon dioxide and silicon dioxide-based low-k dielectric materials, which are typically used in combination with copper material in order to reduce signal propagation delay caused by the parasitic capacitance in the metallization system, a conductive barrier material, such as tantalum, tantalum nitride and the like, is to be formed in the metal lines and vias.
Since reliability and lifetime of complex semiconductor devices may essentially be determined by the duration of metallization systems, significant efforts are being made in investigating line degradation in metallization systems caused by electromigration, since a complex interaction between dielectric materials, the highly conductive core material, such as copper, and the geometry of conductive parts may have to be taken into consideration in order to quantitatively estimate the overall performance and degradation over lifetime.
With reference to FIGS. 1a-1c, a typical electromigration mechanism may be explained in a metal-based interconnect system of a semiconductor device.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, i.e., any appropriate carrier material, such as a semiconductor substrate and the like. Moreover, a device level 110, which may be understood as a semiconductor layer, in and above which a plurality of semiconductor-based circuit elements, such as transistors, resistors and the like, are provided, may be formed above the substrate 101 and may have incorporated therein a plurality of circuit elements, which are schematically indicated by 111. Moreover, a metallization system 150 is provided above the device level 110 and typically comprises a plurality of metallization layers, wherein, for convenience, two metallization layers 160 and 170 are illustrated. The metallization layer 160 typically comprises a dielectric material 161, such as a low-k dielectric material in the form of silicon dioxide-based materials having a reduced density, thereby obtaining a reduced dielectric constant of 3.0 and less. In other cases, any other appropriate dielectric materials, such as polymer materials and the like, may be used as the dielectric material 161. Moreover, the metallization layer 160 comprises a plurality of metal lines, wherein, for convenience, a single metal line 163 is illustrated. As discussed above, the metal line 163 comprises a highly conductive metal 163A, such as aluminum, and, in sophisticated applications, copper, in which case, a conductive barrier material 163B is also required, which may, thus, substantially suppress diffusion of copper into the dielectric material 161 and, which may also suppress the incorporation of reactive atomic species, such as fluorine, oxygen and the like, into the highly conductive core metal 163A. Moreover, the metallization layer 160 may comprise an etch stop material 162, which, in some cases, may also act as a diffusion blocking layer for confining the material 163A of the metal line 163. For example, silicon nitride-based materials or silicon oxide-based materials may be used.
The metallization layer 170 comprises a dielectric material 171, a metal line 173L in combination with a via 173V, which comprise a highly conductive metal 173A, possibly in combination with a conductive barrier material 173B. Furthermore, a cap layer or etch stop layer 172 is formed on the dielectric material 171 and may, depending on the overall process strategy, act as a confinement cap layer for the metal line 173L. Basically, the same materials may be used in the metallization layer 170 for the various components as is also described for the metallization layer 160.
Upon operating the device 100, a current flow may be established in the flow path, a portion of which is represented by the metal line 163, the via 173V and the metal line 173L. For example, it may be assumed that the electron flow is directed from the metal line 163 to the metal line 173L. As previously explained, electromigration is a highly complex dynamic process, in which the momentum exchange between charge carriers, that is, electrons, and metal atoms may result in a collective migration of the metal atoms when a sufficiently high current density is achieved. Due to the reduced cross-sectional areas of the metal lines 163, 173L and the via 173V in sophisticated integrated circuits, and due to the fact that, in principle, the metal lines are confined in a respective dielectric material allowing a very efficient heat transfer into the surrounding chip area, extremely high current densities of approximately 106 ampere per cm2 may be achieved, thereby resulting in significant electromigration effects. Thus, unless the metallization structure of a semiconductor device is designed and manufactured in such a way that such high current densities may be reliably avoided in any metal region of the semiconductor device, electromigration will occur during the operation of the semiconductor device 100. It should be appreciated that a design of semiconductor devices, in which any such high current densities may be avoided, would significantly reduce the design flexibility and would require a reduced packing density, thereby also reducing performance and cost efficiency of any such semiconductor devices. Consequently, typically, a compromise is made between performance and packing density with respect to electromigration in that, instead of manufacturing substantially “immortal” metallization structures, design and manufacturing criteria are selected such that a desired lifetime under specific operation conditions is achieved. Certain theoretical models of the electromigration phenomenon have been established, for instance known under Black's Law, which indicate a relationship between a typical time to failure and the square of the inverse current density and which quantitatively describes the effect of electromigration for a certain class of conditions with moderate precision. Moreover, other effects, such as the Blech effect, have been discovered, which allows completely avoiding electromigration effects, when the length of a metal region at a specific current density is selected to be equal or less than a critical length.
Consequently, based on theoretical models and appropriately designed test structures, critical portions in the metallization system may be determined and the time to failure may be estimated. That is, due to the diffusion in the metal lines and vias, voids may be formed in one area of the metal line, thereby continuously increasing the overall resistivity, which may, thus, contribute to an even further increased current density, which may finally result in a complete failure of the corresponding interconnect structure.
FIG. 1b schematically illustrates an electromigration effect in the metallization system 150. For example, it may be assumed that the barrier layer 163B at the bottom of the via 173V may represent a strong barrier, thereby suppressing any metal diffusion from the line 163 into the via 173V. In this case, upon establishing the current flow, as indicated, electromigration may occur in the via 173V and the metal line 173L, wherein, increasingly, the metal, for instance copper, may be transported along the current flow direction. However, the diffused metal has to be accumulated within the metal lines if a corresponding strong barrier is present, thereby increasing and densifying the material in the metal lines, which may, thus, result in an increasing compressive stress. For example, a corresponding “enrichment” with additional metal material in the downstream direction may result in a consumption of grain boundaries 174G, thereby increasing the average size of the metal grains in the downstream direction, while increasingly causing a material depletion in the upstream direction.
FIG. 1c schematically illustrates the situation after a significant amount of metal material has been transported along the via 173V and the metal line 173L, thereby resulting in a reduced number of grain boundaries 174G and, thus, in a reduced number of metal grains, while at the same time a certain degree of voiding, indicated by a void 175, has occurred.
Consequently, upon designing metal fuses, the per se negative effect of electromigration may be used in order to cause a permanent line degradation in a corresponding metal fuse by intentionally providing a portion or fuse body subjected to increased electromigration, which, for instance, may be accomplished, according to Blech's Law, on the basis of a sufficient length for a given available current density, which in turn may be determined by a cross-sectional area of the metal line portion and the available programming voltage and current. Due to the high conductivity of the metal lines, however, high currents and/or an increased length of the fuse body may be required, thereby reducing the “packing density” of corresponding metal fuses in the metallization system of complex semiconductor devices.
The present disclosure is directed to various devices and methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.